When we write SystemVerilog, we often need to represent digital data in our code.

In this post, we look at both the older verilog data types and the newer SystemVerilog types.

In addition to this, a number of new types were introduced as a part of the SystemVerilog standard.

When we assign data to a signal in SystemVerilog, the data is implicitly converted to the correct type in most cases.Īs a result, there is often no need necessary to explicitly perform type conversions in verilog.Īs SystemVerilog is an extension of verilog, we can use all of the existing verilog data types in our code. We can also use types which interpret our data as if it were a numeric value. We can use types which interpret data purely as a logical value, for example. The type which we specify is used to define the characteristics of our data. This includes a discussion of data representation, 2 state vs 4 state types, binary data types and numerical data types.Īlthough SystemVerilog is considered to be a loosely typed language, we must still declare a data type for every port or signal in our SystemVerilog design. In this post, we talk about the most commonly used data types in SystemVerilog.